This invention relates to CMOS clock buffers, and more particularly to low-noise controlled-slope clock buffers.
Significant advances in semiconductor process technology have allowed for large numbers of transistors to be integrated together on large-scale-integration (LSI) integrated circuits (ICs). These LSI chips typically use complementary metal-oxide-semiconductor (CMOS) process technology. Synchronous designs such as state machines are often employed, requiring clocks to be distributed over the chip to latch elements.
Large, high-current-drive clock buffers are needed to drive the large capacitive load of the clock inputs to the many latch elements, and the long metal clock-line traces. Higher current drive increases speed because load capacitances are more quickly charged or discharged. Unfortunately, unwanted interference and noise often increase too.
The high density of these LSI chips is in part due to tight spacing among metal traces. Adjacent metal traces can pick up noise from clock lines by capacitive coupling of rapid voltage changes. Such electromagnetic interference (EMI) tends to increase as higher densities and faster transistors are used.
The rate of voltage change of the clock signal, the edge rate, increases for these faster devices. The high edge rate transition can also reflect off the ends of metal wiring traces driven by the clock buffer. These reflections produce voltage variations known as undershoot, overshoot, and ringing (oscillation).
FIG. 1 is a diagram of a waveform of a prior-art high-drive clock buffer driving a long metal wiring trace. The high current drive of the clock buffer produces a high edge rate which rapidly changes the clock line voltage from ground to the power-supply voltage, Vcc. The high edge rate produces EMI interference with other adjacent metal traces, causing voltage changes on these adjacent lines. Ringing due to reflections can also occur on the clock line.
The EMI can be reduced by slowing down the edge of the clock transition, such as by using a weaker clock driver. However, the weaker clock driver will then be more susceptible to jitter from sources such as supply noise. The clock edge requires more time to pass through the switching threshold, causing greater noise susceptibility. Of course, the weaker clock driver also increases clock delay and thus slows down the chip.
The co-inventor has solved a somewhat related problem of ground bounce on output buffers by pulsing large output driver transistors on and off. See xe2x80x9cA High-Drive CMOS Output Buffer with Noise Supression Using Pulsed Drivers and Neighbor-sensingxe2x80x9d, by Kwong, U.S. Pat. No. 5,717,343, assigned to Pericom Semiconductor Corp. of San Jose, Calif. The output is driven by both large and small transistors. The small transistors are enabled and disabled normally by inverters. However, the larger driver transistors are pulsed on just briefly at the start of a transition, and are quickly disabled at the mid-point of the transition.
FIG. 2 is a waveform of an output buffer that enables the larger transistors only during the first part of the voltage transition. When internal input signal IN changes, indicating that the output should change, the large driver transistor is enabled. Signal ENA-UP"" drives the gate of a large PMOS pull-up transistor, while signal ENA-DOWN drives the gate of a large NMOS pull-down transistor. As the output voltage reaches the logic switching threshold, about Vcc divided by 2, the large driver transistor is disabled and the smaller driver transistor continues to drive the signal to either power or ground. The rate of voltage change is reduced as the output voltage approaches the power-supply or ground voltage. This reduction in edge rate occurs after the switching threshold is reached, and thus does not slow down switching delays. The softer edge reduces the reflection and thus ringing, overshoot, and undershoot are also reduced.
What is desired is a clock buffer with high current drive and high speed but reduced EMI. It is desired to reduce jitter on the clock by rapidly switching the clock output near the switching threshold, but still reduce EMI by more slowly switching the output away from the switching threshold. It is desired to reduce induced EMI from the fast edge rate. It is desired to dynamically control the edge rate of the clock buffer to provide high drive and rapid voltage change near the receiver""s switching threshold, but lower drive and a slower voltage change for the remainder of the transition. It is further desired to pulse large driver transistors on only during the middle of the transition so that the large driver transistors are off at the start and at the end of the transition.
A reduced-jitter and reduced-electro-magnetic interference (EMI) clock driver has a clock input, a clock output, and a driver p-channel transistor with a source coupled to a power supply and a drain coupled to the clock output and a gate coupled to a first gate node. A weak p-channel transistor has a source coupled to the power supply and a drain coupled to the clock output and a gate coupled to a weak-gate node. The weak-gate node is buffered from the clock input by at least one inverter.
A first large inverter drives a first pass node with an inverse of the clock input. A first pulsing circuit is responsive to the clock input. It generates a first pulse when the clock input changes from low to high logic states. A first pass transistor has a gate that receives the first pulse. It connects the first pass node to the first gate node in response to the first pulse.
A first disable transistor is coupled to the first gate node. It drives a disabling voltage onto the first gate node when the first pulse is not active. A driver n-channel transistor has a source coupled to a ground and a drain coupled to the clock output and a gate coupled to a second gate node. A weak n-channel transistor has a source coupled to the ground and a drain coupled to the clock output and a gate coupled to the weak-gate node.
A second large inverter drives a second pass node with an inverse of the clock input. A second pulsing circuit is responsive to the clock input. It generates a second pulse when the clock input changes from high to low logic states.
A second pass transistor has a gate receiving the second pulse. It connects the second pass node to the second gate node in response to the second pulse. A second disable transistor is coupled to the second gate node. It drives a disabling voltage onto the second gate node when the second pulse is not active. Thus driver transistors are pulsed.
In further aspects of the invention, pulsing the driver n-channel and p-channel transistors reduces jitter near a mid-point of a transition by increasing a voltage-slew rate near the mid-point, but reduces overall EMI by disabling the n-channel and p-channel driver transistors before and after the mid-point. Thus jitter and EMI are reduced.
In still further aspects, the driver n-channel transistor has a larger current drive than the weak n-channel transistor. The driver p-channel transistor has a larger current drive than the weak p-channel transistor.